From 72ac6dab9f283d9000ae140fc41908fa3393bc21 Mon Sep 17 00:00:00 2001
From: Max Zhen <max.zhen@amd.com>
Date: Mon, 13 Apr 2026 16:24:04 -0700
Subject: [PATCH] fix compilation errors with gcc 16

Signed-off-by: Max Zhen <max.zhen@amd.com>
--- a/src/shim/umq/dbg_hwq.cpp
+++ b/src/shim/umq/dbg_hwq.cpp
@@ -95,8 +95,8 @@ submit()
   *m_dbg_umq_comp_ptr = 0;
 
   /* Issue mfence instruction to make sure all writes to the slot before is done */
-  std::atomic_thread_fence(std::memory_order::memory_order_seq_cst);
-  m_dbg_umq_hdr->write_index++;
+  std::atomic_thread_fence(std::memory_order_seq_cst);
+  m_dbg_umq_hdr->write_index = m_dbg_umq_hdr->write_index + 1;
 
   shim_debug("dbg umq: submit cmd widx: %lu ridx: %lu",
     m_dbg_umq_hdr->write_index,
--- a/src/shim/umq/hwq.cpp
+++ b/src/shim/umq/hwq.cpp
@@ -226,10 +226,11 @@ issue_single_exec_buf(const cmd_buffer *cmd_bo, bool last_of_chain)
   // TODO: remove once uC stops looking at and updating this field.
   hdr->common_header.type = HOST_QUEUE_PACKET_TYPE_VENDOR_SPECIFIC;
   // Issue mfence instruction to make sure all writes to the slot before is done.
-  std::atomic_thread_fence(std::memory_order::memory_order_seq_cst);
+  std::atomic_thread_fence(std::memory_order_seq_cst);
   // Indicates the slot is ready for processing by uC.
   // Must be the last step after pkt is filled up.
-  uint64_t wi = m_umq_hdr->write_index++;
+  uint64_t wi = m_umq_hdr->write_index;
+  m_umq_hdr->write_index = wi + 1;
 
   // Wake up uC in case it is sleeping and waiting.
   *m_mapped_doorbell = 0;